The present invention relates generally to memory designs, and more particularly to a method to eliminate soft error rate by error checking and correcting (ECC) mechanisms.
The accumulation of soft errors is a quality limiting factor in semiconductor memories, such as static random access memories (SRAMs). Soft errors are those that occur unpredictably due to external causes. The most typical causes are alpha-particles from environmental sources and cosmic rays from universal sources. As these charged particles penetrate a semiconductor device, pairs of oppositely charged current carriers are generated. These carriers are immediately conducted as photocurrent and their charges are accumulated as spurious data. The march of technology means that components, such as transistors and capacitors, in integrated circuits, and memories are produced in greater numbers and ever smaller sizes. Therefore, the amount of charge that is required to register data has become very small, and the charge induced by the external causes has become more significant than ever. It is now easier to accumulate enough random charges to register spurious data, or soft errors. For example, the accumulation rate of soft error is an increasing problem in advanced semiconductor memories.
Various structures and processes have been proposed to alleviate this problem. One structural solution that has been realized is the addition of capacitors to each storage node of an SRAM. This means that more charge is required to shift the voltage on a storage node and thereby switch the data state that is stored at the node. However, the larger capacitance means not only that more charge is required to intentionally write data to that memory storage node, but also longer memory write time, thereby slowing down the random access speed. In addition, the construction of additional capacitors requires extra expensive processing and memory cell area.
One pure logic solution that has been utilized is the correction of soft errors by an error checking and correcting (ECC) logic circuit during read access cycles. Every time when a memory circuit is accessed for reading data, the ECC logic circuit would check the read data for soft errors. If error data are detected, the corrected data would be written back into the memory circuit. This requires not only 10 to 50 percent extra memory cell area, but also a reduction in access speed because the ECC logic circuit would impose a penalty on the read access cycles. Moreover, soft errors accumulate irregularly, but the ECC logic circuit can only correct them during a normal read access. Absent an operational demand for such access, errors can accumulate beyond the correction capacity of the ECC logic circuit, and those errors will not be corrected. Furthermore, the ECC logic circuit needs extra parity bits for error checking and correcting. For instance. every 8-bit data require extra 4 parity bits for single error correction, that means only one error is allowed to occur with this 12-bit memory cell area. The 4 parity bits would take 50% of the total area for the 8-bit data. This is a cell area penalty.
As technology advances, the occurrence of soft errors increases. Desirable in the art of memory designs are improved methods and systems that will increase soft error immunity without imposing a memory speed penalty, and an error correction capacity penalty due to an undesired accumulation of soft errors.